ADV7481WBBCZ datasheet(20/22 Pages) AD

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ADV7481

Data Sheet

DIAGx pin to sense an STB event on either input, because there

is a minimal voltage drop across the resistor.

Figure 17. Diagnostic Connection for Differential Inputs

Resistors R4 and R5 divide down the voltage at the input

connector to protect the DIAGx pin from an STB event. The

DIAGx pin circuitry compares this voltage to a programmable

reference voltage, known as the diagnostic slice level. When the

diagnostic slice level is exceeded, an STB event has occurred.

R4 and R5 are sized to allow the use of low cost, small footprint

resistors that are tolerant of STB events.

Use the following equation to find the STB voltage for a selected

diagnostic slice level.

_SLICE_LEV

DIAGNOSTIC

STB_TRIGGE

where:

VSTB_TRIGGER is the minimum voltage required at the input

connector to trigger the STB interrupt on the ADV7481.

DIAGNOSTIC_SLICE_LEVEL is the programmable reference

voltage.

For example, with a diagnostic slice level programmed to

1.125 V, an R4 value of 9.1 kΩ, and an R5 value of 1 kΩ, the

minimum voltage required at the input connector to trigger the

STB interrupt is approximately 11.4 V.

When the DIAGx pin voltage exceeds the diagnostic slice level

voltage, a hardware interrupt is triggered and indicated by one

of the interrupt pins. A readback register specifies the input on

which the STB event occurred.

STANDARD DEFINITION PROCESSOR

The ADV7481 is capable of decoding a large selection of

baseband video signals in composite (both single-ended and

differential), S-Video, and component formats. The video

standards supported by the video processor include

• PAL B, PAL D, PAL G, PAL H, PAL I, PAL M, PAL N,

PAL Nc, and PAL 60

• NTSC J, NTSC M, and NTSC 4.43

• SECAM B, SECAM D, SECAM G, SECAM K, and SECAM L

The ADV7481 can automatically detect the video standard and

process it accordingly.

The ADV7481 has a five-line adaptive 2D comb filter that

provides superior chrominance and luminance separation when

decoding a composite video signal. This highly adaptive filter

automatically adjusts its processing mode according to the

video standard and signal quality without requiring user

intervention. Video user controls such as brightness, contrast,

saturation, and hue are also available with the ADV7481.

The ADV7481 implements the patented Adaptive Digital Line

Length Tracking (ADLLT™) algorithm to track varying video

line lengths from sources such as a VCR. ADLLT enables the

ADV7481 to track and decode poor quality video sources such

as VCRs and noisy sources from tuner outputs, VCD players,

and camcorders. The ADV7481 contains a chroma transient

improvement (CTI) processor that sharpens the edge rate of

chroma transitions, resulting in sharper vertical transitions.

The ACE of the ADV7481 offers improved visual detail using

an algorithm that automatically varies contrast levels to enhance

picture detail. ACE allows the contrast of an image to increase

depending on the content of the picture. Typically, this allows

bright areas to be made brighter and dark areas to be made

darker. However, the ADV7481 ACE feature also allows the

contrast within dark areas to increase without significantly

affecting the bright areas of the picture. This feature is

particularly useful in automotive applications, where it is

important to discern objects in shaded areas.

Downdithering converts the output of the ADV7481 from an 8-

bit to a 6-bit output, enabling ease of design for standard LCD

panels.

The SDP can process a variety of VBI data services, such as

closed captioning (CCAP), wide screen signaling (WSS), and

copy generation management system (CGMS).

The ADV7481 is fully Rovi® (Macrovision®) compliant;

detection circuitry enables Type I, Type II, and Type III

protection levels to be identified and reported to the user. The

decoder is also fully robust to all Macrovision signal inputs.

8-BIT DIGITAL INPUT/OUTPUT PORT

The ADV7481 features an 8-bit digital bidirectional port. The

following formats are supported both as input and output ports:

•

8-bit interleaved 4:2:2 SDR input/output with embedded

timing codes

•

8-bit interleaved 4:2:2 DDR input/output with embedded

timing codes

The maximum input and output video resolution supported is

720p/1080i in both SDR and DDR modes.

Video received on the 8-bit digital input port can be routed to

the four-lane MIPI CSI-2 transmitter. Video sent on the 8-bit

digital output port can be routed from either the SD core or the

CP core.

AINx

AINy

ANALOG INPUT

CVBS_P

CVBS_N

1.3kΩ

75Ω

150Ω

430Ω

DIAGx

100nF

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