Data Sheet

ADV7482

TIMING SPECIFICATIONS

AVDD = 1.71 V to 1.89 V, DVDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, MVDD = 1.71 V to 1.89 V, CVDD = 1.71 V to 1.89 V,

DVDDIO = 3.14 V to 3.46 V, and TVDD = 3.14 V to 3.46 V, specified at operating temperature range, unless otherwise noted.

Table 5.

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

CLOCK AND CRYSTAL

Nominal Frequency1

Required by design

28.63636

MHz

Frequency Stability1

Required by design

±50

ppm

Input LLC Clock Frequency

Range2, 3

DVDDIO = 3.14 V to 3.46 V

13.5

148.5

MHz

Output LLC Clock Frequency

Range2,3

DVDDIO = 3.14 V to 3.46 V

13.5

148.5

MHz

I2S_SCLK Frequency3

12.288

MHz

I2S_MCLK Frequency3

24.576

MHz

SCLK Frequency

400

kHz

SCLK Minimum Pulse Width High

0.6

µs

SCLK Minimum Pulse Width Low

1.3

µs

Hold Time (Start Condition)

0.6

µs

Setup Time (Start Condition)

0.6

µs

SDATA Setup Time

100

ns

SCLK and SDATA Rise Times

300

ns

SCLK and SDATA Fall Times

300

ns

Setup Time (Stop Condition)

0.6

µs

RESET FEATURE

RESET Pulse Width1

5

ms

8-BIT DIGITAL INPUT PORT2

DVDDIO = 3.14 V to 3.46 V

LLC High Time3

45

55

% duty

cycle

LLC Low Time3

45

55

% duty

cycle

SDR and DDR Modes Setup Time

Data latched on rising edge

1

ns

SDR and DDR Modes Hold Time

Data latched on rising edge

1

ns

DDR Mode Setup Time

Data latched on falling edge

1

ns

DDR Mode Hold Time

Data latched on falling edge

1

ns

8-BIT DIGITAL OUTPUT PORT2

DVDDIO = 3.14 V to 3.46 V

LLC High Time

40

60

% duty

cycle

LLC Low Time

40

60

% duty

cycle

SDR Modes Setup Time4, 5

At P0 to P7 output pin, data latched on rising

edge

1.98

ns

SDR Modes Hold Time4, 5

At P0 to P7 output pin, data latched on rising

edge

2.50

ns

DDR Modes Setup Time4, 5

At P0 to P7 output pin, data latched on rising

edge

1.66

ns

DDR Modes Hold Time4, 5

At P0 to P7 output pin, data latched on rising

edge

3.52

ns

DDR Mode Setup TIme4, 5

At P0 to P7 output pin, data latched on falling

edge

1.71

ns

DDR Modes Hold Time4, 5

At P0 to P7 output pin, data latched on falling

edge

3.17

ns

Rev. 0 | Page 9 of 20