ADV7604

Data Sheet

Rev. D | Page 4 of 20

SPECIFICATIONS

AVDD = 1.8 V ± 5%, DVDD = 1.8 V ± 5%, DVDDIO = 3.3 V ± 5%, PVDD = 1.8 V ± 5%, TVDD = 3.3 V ± 5%, CVDD = 1.8 V ± 5%,

ANALOG, DIGITAL, HDMI, AND AC SPECIFICATIONS

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ANALOG

Clamp Circuitry

External Clamp Capacitor

100

nF

Input Impedance

Clamps switched off

10

MΩ

ADC Midscale (CML)

0.89

V

ADC Full-Scale Level

CML + 0.550

V

ADC Zero-Scale Level

CML − 0.550

V

ADC Dynamic Range

1.1

V

Clamp Level (WhenLocked)

Component input (Y signal)

CML − 0.130

V

Component input (Pr signal)

CML

V

Component input (Pb signal)

CML

V

PC RGB input (R, G, B)

CML − 0.130

V

DIGITAL INPUTS

2

V

0.8

V

RESET pin

−60

+60

µA

Other digital inputs

−10

+10

µA

10

pF

DIGITAL INPUTS (5 V TOLERANT)1

2.6

V

0.8

V

SHARED_EDID pin

−150

+60

µA

Other 5 V digital inputs

−82

+82

µA

DIGITAL OUTPUTS

2.4

V

0.4

V

10

µA

20

pF

HDMI

TMDS Differential Pin Capacitance

0.3

pF

AC SPECIFICATIONS

Intrapair (+ to −) Differential Input Skew for TMDS

Clock Rates up to 222.75 MHz

ps

Intrapair (+ to −) Differential Input Skew for TMDS

Clock Rates Above 222.75 MHz

+ 112

ps

Channel-to-ChannelDifferentialInput Skew

1.78

ns

TMDS Input Clock Range

25

225

MHz

Input Clock Jitter Tolerance

0.5

1

The following pins are 5 V tolerant: HS_IN1, HS_IN2, VS_IN1, VS_IN2, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL, DDCC_SDA, DDCD_SCL, DDCD_SDA,

RXA_5V, RXB_5V, RXC_5V, RXD_5V, SHARED_EDID, PWRDN, EP_MISO.