WM8983 datasheet(73/129 Pages) CIRRUS

73 / 129 page

WM8983

Rev 4.6

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R49

Output control

SPKBOOST

Speaker Gain

0 = speaker gain = -1;

DC = AVDD1 / 2

1 = speaker gain = +1.5;

DC = 1.5 x AVDD1 / 2

Power

management

BUFDCOPEN

Output stage 1.5xAVDD/2 driver

enable

0 = Buffer disabled

1 = Buffer enabled (required for 1.5x

gain boost)

Table 43 Speaker Boost Stage Control

SPKBOOST

OUTPUT

STAGE GAIN

OUTPUT DC

LEVEL

OUTPUT STAGE

CONFIGURATION

1x (0dB)

AVDD1/2

Inverting

1.5x (3.52dB)

1.5xAVDD1/2

Non-inverting

Table 44 Output Boost Stage Details

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R43

Beep control

INVROUT2

Invert ROUT2 output

0 = Not inverted

1 = Inverted

Table 45 ROUT2 Phase Invert Control

ZERO CROSS TIMEOUT

A zero-cross timeout function is provided so that if zero cross is enabled on the input or output PGAs,

the gain will automatically update after a timeout period if a zero cross has not occurred. This is

enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital

and is equal to 221 * SYSCLK period.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Additional

Control

SLOWCLKEN

Slow clock enable.

Used for both the jack insert detect

debounce circuit and the zero cross

timeout.

0 = slow clock disabled

1 = slow clock enabled

Table 46 Timeout Clock Enable Control

Note: SLOWCLKEN is also used for the jack insert detect debounce circuit

WM8983 Datasheet(PDF) 73 Page - Cirrus Logic

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