FUSB307BMPX datasheet(47/57 Pages) ONSEMI

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Table 52. RXDETECT (continued)

RXDETECT enables the types of messages and/or signaling to be detected. SOP* enabling also turns on auto−GoodCRC response.

This register is reset when: A Hard Reset is received or sent; after the GoodCRC transmission due to RxOneMore; on a disconnect

detection; SW_RST or POR.

Address: 2Fh

Reset Value: 0x00

Type: Read/Write

Bit #

Receive Detect Description (Note 35)

Size (Bits)

R/W/C

Name

EN_SOP2

R/W

0b: Do not detect SOP” message (default)

1b: Detect SOP” message

EN_SOP1

R/W

0b: Do not detect SOP’ message (default)

1b: Detect SOP’ message

EN_SOP

R/W

0b: Do not detect SOP message (default)

1b: Detect SOP message

35. Writing all 0s to this register disables PD.

Table 53. RXBYTECNT

Address: 30h

Reset Value: 0x00

Type: Read

Bit #

Name

R/W/C

Size (Bits)

Received Byte Count Description

7:0

RXBYTECNT

Number of Bytes Received. This is the number of bytes in RXDATA

plus 3 (RXSTAT and RXHEADL, H)

Table 54. RXSTAT

This register indicates the status of the received SOP* message in RXHEADL,RXHEADH, and RXDATA registers.

Address: 31h

Reset Value: 0x00

Type: Read

Bit #

Name

R/W/C

Size (Bits)

Receive Status Description

7:3

Reserved

Reserved: 00000b

2:0

RXSOP

Received SOP

000b: Received SOP

001b: Received SOP’

010b: Received SOP’’

011b: Received SOP’_DBG

100b: Received SOP”_DBG

110b: Received Cable Reset

All others are reserved.

Table 55. RXHEADL

Received Header Low byte is stored here. Expected GoodCRC messages are not stored.

Address: 32h

Reset Value: 0x00

Type: Read

Bit #

Name

R/W/C

Size (Bits)

Receive Header Low Description

7:0

RXHEADL

Rx Header Data Low

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