| Electronic Components Datasheet Search |
|
HMC987LP5E Datasheet(PDF) 21 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
HMC987LP5E Datasheet(HTML) 21 Page - Analog Devices |
|
21 / 24 page ![]() For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Application Support: Phone: 978-250-3343 or apps@hittite.com 21 HMC987LP5E v03.1112 LOW NOISE 1:9 FANOUT BUFFER DC - 8 GHz An example of the two cycle procedure to read from any random address is as follows: the Master (host), on the irst 9 falling edges of sClk places 9 bit data, d8:d0, Msb irst, on sDi as shown in Figure 39. d8:d0 should be set to zero. d3:d0 = address of the register to be rEAD on the next cycle. a. the slave () shifts in data on sDi on the irst 9 rising edges of sClk b. Master places 4 bit register address , r3:r0, ( the address the WritE ADDrEss register), Msb irst, on the next 4 falling edges of sClk (10-13). r3:r0=0000. c. slave shifts the register bits on the next 4 rising edges of sClk (10-13). d. Master places 3 bit chip address, a2:a0, Msb irst, on the next 3 falling edges of sClk (14-16). the chip address is ixed at 001. e. slave shifts the chip address bits on the next 3 rising edges of sClk (14-16). f. Master asserts sEn after the 16th rising edge of sClk. g. slave registers the sDi data on the rising edge of sEn. h. Master clears sEn to complete the address transfer of the two part rEAD cycle. i. if we do not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on sDi to register zero on the rEAD back part of the cycle. j. Master places the same sDi data as the previous cycle on the next 16 falling edges of sClk. k. slave () shifts the sDi data on the next 16 rising edges of sClk. l. slave places the desired data (i.e. data from address in reg00h[3:0]) on sDo on the next 16 rising edges of sClk. m. Master asserts sEn after the 16th rising edge of sClk to complete the cycle. note that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the sDo output to prevent a possible bus contention issue. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. For price, delivery, and to place orders: Analog Devices, Inc., One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 Phone: 781-329-4700 • Order online at www.analog.com Application Support: Phone: 1-800-ANALOG-D |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |