MLX90621

16x4 IR array

Datasheet

39001090621

Page 28 of 44

Datasheet IR16x4

Rev 3.0

15 September 2016

POR

8.3.

The Power On Reset (POR) is connected to the Vdd supply. The on-chip POR circuit provides an active level of the

POR signal when the Vdd voltage rises above approximately 0.5V and holds the entire Mlx90621 in reset until the

Vdd is higher than 2.4V. The device will start approximately 5ms after the POR release.

ESD

8.4.

ESD, 4KV Human Body Model (please check with electrical specification)

Communication protocol

9.

The device supports Fast Mode Plus I

kHz) and will work in slave mode only.

The master device must provide the clock signal (SCL) for the communication. The data line SDA is bidirectional and

is driven by the master or the slave depending on the command. The selection of the SDA occupant is done

according to the I

‘1’ just by releasing it. During data transfer, the data line could be changed only while SCL is low. Otherwise, it would

be interpreted as a start/stop condition

Communication pins

9.1.

There are two communication pins SCL and SDA. SCL is an input only for the MLX90621 while the SDA pin is a

bidirectional one. The SDA line should be wired in an open-drain configuration.

Figure 17 Communication pin diagram

scl_in

SCL (Serial Clock Line )

SDA (Serial data Line )

Rp

Rp

90670

sda_in

sda_out

90670

Digital

Block

SCL

SDA

External I2C

Master

SCL

SDA

24AA02

90620

+VDD

external

90621