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PIN CONFIGURATIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

MSB

RS

CS

CLK

SDI

DGND

LDAC

SDO

DAC8814

(TOP VIEW)

NOTE (1): NC − No internal connection

DAC8814

SBAS338 – JANUARY 2005

PIN DESCRIPTION

PIN

NAME

DESCRIPTION

1, 14, 15, 28

2, 13, 16, 27

DAC A, B, C, D Current output.

DAC A, B, C, D Reference voltage input terminal. Establishes DAC A, B, C, D full-scale

3, 12, 17, 26

4, 11, 18, 25

Establish voltage output for DAC A, B, C, D by connecting to external amplifier output.

5

MSB

Reset pin, active low. Input register and DAC registers are set to all zeros or half scale

6

RS

code (8000h) determined by the voltage on the MSB pin. Register data = 8000h when

MSB = 1.

7

Positive power supply input. Specified range of operation 5 V

±10%.

Chip-select; active low input. Disables shift register loading when high. Transfers shift

8

CS

register data to input register when CS/LDAC goes high. Does not affect LDAC operation.

9

CLK

Clock input; positive edge triggered clocks data into shift register

10

SDI

Serial data input; data loads directly into the shift register.

19

NC

Not connected; leave floating.

Serial data output; input data loads directly into shift register. Data appears at SDO, 19

20

SDO

clock pulses after input at the SDI pin.

Load DAC register strobe; level sensitive active low. Tranfers all input register data to the

21

LDAC

DAC registers. Asynchronous active low input. See Table 1 for operation.

22

High current analog force ground.

23

Negative bias power-supply input. Specified range of operation -0.3 V to -5.5 V.

24

DGND

Digital ground.

5