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D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

A0

A1

A

B

C

D

ADC

2:4

Decode

Input

Register R

Input

Register R

Input

Register R

Input

Register R

DAC A

Register R

DAC B

Register R

DAC C

Register R

DAC D

Register R

DAC A

DAC B

DAC C

DAC D

Set MSB

Set

MSB

Power-

on

Reset

DGND

MSB

LDAC

RS

A B C D

CS

CLK

SDI

SDO

EN

SERIAL DATA INTERFACE

DAC8814

SBAS338 – JANUARY 2005

Figure 56. System Level Digital Interfacing

The DAC8814 uses a 3-wire (CS, SDI, CLK) SPI-compatible serial data interface. Serial data of the DAC8814 is

clocked into the serial input register in an 16-bit data-word format. MSB bits are loaded first. Table 2 defines the

16 data-word bits for the DAC8814.

Data is placed on the SDI pin, and clocked into the register on the positive clock edge of CLK subject to the data

setup and data hold time requirements specified in the Interface Timing Specifications. Data can only be clocked

in while the CS chip select pin is active low. For the DAC8814, only the last 16 bits clocked into the serial register

are interrogated when the CS pin returns to the logic high state.

Since most microcontrollers output serial data in 8-bit bytes, three right-justified data bytes can be written to the

DAC8814. Keeping the CS line low between the first, second, and third byte transfers results in a successful

serial register update. Similarly, two right-justified data bytes can be written to the DAC8814. Keeping the CS line

low between the first and second byte transfer will result in a successful serial register update.

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