AD9737ABBCZ datasheet(46/64 Pages) AD

46 / 64 page

AD9737A/AD9739A

Data Sheet

Rev. D | Page 46 of 64

CLK INPUT COMMON MODE

Table 23. CLK Input Common Mode Register (CROSS_CNT1 and CROSS_CNT2)

Address

(Hex)

Bit Name

Bits

R/W

Default

Setting

Description

0x22

DIR_P

R/W

0x0

DIR_P and DIR_N.

0 = VCM at the DACCLK_P input decreases with the offset value.

1 = VCM at the DACCLK_P input increases with the offset value.

CLKx_OFFSET sets the magnitude of the offset for the DACCLK_P and

DACCLK_N inputs. For optimum performance, set to 1111.

CLKP_OFFSET[3:0]

[3:0]

R/W

0x0000

0x23

DIR_N

R/W

0x0

CLKN_OFFSET[3:0]

[3:0]

R/W

0x0000

MU CONTROLLER CONFIGURATION AND STATUS

Table 24. Mu Controller Configuration and Status Register (PHS_DET, MU_DUTY, MU_CNT[1:4], and MU_STAT1)

Address

(Hex)

Bit Name

Bits

R/W

Default

Setting

Description

0x24

CMP_BST

R/W

0x0

Phase detector enable and boost bias bits.

PHS_DET

AUTO_EN

R/W

0x0

Note that both bits should always be set to 1 to enable these functions.

0x25

MU_

DUTYAUTO_EN

R/W

0x0

Mu controller duty cycle enable.

Note that this bit should always be set to 1 to enable.

0x26

Slope

R/W

0x1

Mu controller phase slope lock. 0 = negative slope, 1 = positive slope. Note

that a setting of 0 is recommended for best ac performance.

Mode[1:0]

[5:4]

R/W

0x00

Sets the Mu controller mode of operation.

00 = search and track (recommended).

01 = search only.

10 = track.

Read

R/W

0x0

Set to 1 to read the current value of the Mu delay line in.

Gain[1:0]

[2:1]

R/W

0x01

Sets the Mu controller tracking gain.

Recommended to leave at the default 01 setting.

Enable

R/W

0x0

0 = disable the Mu controller.

1 = enable the Mu controller.

0x27

MUDEL[0]

R/W

0x0

The LSB of the 9-bit MUDEL setting.

SRCH_MODE[1:0]

[6:5]

R/W

0x0

Sets the direction in which the Mu controller searches (from its initial MUDEL

setting) for the optimum Mu delay line setting that corresponds to the desired

phase/slope setting (that is, SET_PHS and slope ).

00 = down.

01 = up.

10 = down/up (recommended).

SET_PHS[4:0]

[4:0]

R/W

0x0

Sets the target phase that the Mu controller locks to with a maximum setting

of 16.

A setting of 4 (that is, 00100) is recommended for optimum ac performance.

0x28

MUDEL[8:1]

[7:0]

0x00

With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the

value that the Mu delay is set to. Note that the maximum value is 432.

With enable set to 1, this value represents the Mu delay value at which the

controller begins its search. Setting this value to the delay line midpoint of

216 is recommended.

0x00

When read (Bit 3, Register 0x26) is set to 1, the value read back is equal to

the value written into the register when enable = 0 or the value that the

Mu controller locks to when enable = 1.

AD9737ABBCZ Datasheet(PDF) 46 Page - Analog Devices

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