AD5693RARMZ datasheet(22/26 Pages) AD

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AD5693R/AD5692R/AD5691R/AD5693

Data Sheet

Rev. D | Page 22 of 26

The output stage is shown in Figure 48.

RESISTOR

NETWORK

VOUT

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 48. Output Stage During Power-Down

The output amplifier is shut down when the power-down mode

is activated. However, unless the internal reference is powered

down (using Bit DB12 in the control register), the bias

generator, reference, and resistor string remain on. The supply

current falls to 2 μA at 5 V. The contents of the DAC register are

unaffected when in power-down mode, and the DAC register can

continue to be updated. The time that is required to exit power-

down is typically 4 µs for VDD = 5 V, or 600 µs if the reference is

disabled.

Reset Bit

The AD5693R/AD5692R/AD5691R/AD5693 control register

contains a software reset bit that resets the DAC to zero-scale and

resets the input, DAC, and control registers to their default values.

A software reset is initiated by setting the RESET bit in the

control register to 1. When the software reset has completed,

the reset bit is cleared to 0 automatically.

READ OPERATION

When reading the input register back from the AD5693R/

AD5692R/AD5691R/AD5693 DACs, the user begins with an

address byte (R/W = 1), after which the DAC acknowledges that

it is prepared to receive data by pulling SDA low. Two bytes of

data containing the contents of the input register are then read

from the DAC, as shown in Figure 49. A NACK condition from

the master followed by a STOP condition completes the read

sequence.

SCL

SDA

START BY

MASTER

FRAME 1

SLAVE ADDRESS

FRAME 3

DATA HIGH BYTE

FRAME 2

COMMAND BYTE

ACK BY

AD5693R/AD5692R/AD5691R/AD5693

NACK BY

MASTER

STOP BY

MASTER

ACK BY MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R/W

Figure 49. I2C Read Operation

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