AD5722R/AD5732R/AD5752R

Data Sheet

Rev. F | Page 2 of 32

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Performance Characteristics ................................................ 5

Timing Characteristics ................................................................ 6

Timing Diagrams.......................................................................... 7

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Architecture................................................................................. 20

Serial Interface ............................................................................ 20

Load DAC (LDAC)..................................................................... 22

Asynchronous Clear (CLR)....................................................... 22

Configuring the AD5722R/AD5732R/AD5752R .................. 22

Transfer Function ....................................................................... 22

Input Shift Register .................................................................... 26

DAC Register .............................................................................. 27

Output Range Select Register ................................................... 27

Control Register ......................................................................... 28

Power Control Register.............................................................. 28

Design Features............................................................................... 29

Analog Output Control ............................................................. 29

Power-Up Sequence ................................................................... 20

Power-Down Mode .................................................................... 29

Overcurrent Protection ............................................................. 29

Thermal Shutdown .................................................................... 29

Internal Reference ...................................................................... 29

Applications Information .............................................................. 30

+5 V/±5 V Operation ................................................................ 30

Layout Guidelines....................................................................... 30

Galvanically Isolated Interface ................................................. 31

Microprocessor Interfacing....................................................... 31

Outline Dimensions ....................................................................... 32

Ordering Guide .......................................................................... 32

REVISION HISTORY

2/2017—Rev. E to Rev. F

Added Power-Up Sequence Section............................................. 20

Changes to Table 8 and Table 9..................................................... 23

Changes to Table 11 and Table 12 ................................................ 24

Changes to Table 14 and Table 15 ................................................ 25

Change to Analog Output Section ............................................... 29

Added Alternative Power-Up Sequence Support Section ......... 30

2/2016—Rev. D to Rev. E

Changes to Table 1............................................................................ 3

7/2011—Rev. C to Rev. D

Changes to Table 4: t7, t8, t10 Limits....................................................... 6

3/2011—Rev. B to Rev. C

Changes to Configuring the AD5722R/AD5732R/

AD5752R Section ........................................................................... 22

8/2010—Rev. A to Rev. B

Changes to Table 28 ....................................................................... 28

4/2010—Rev. 0 to Rev. A

Changes to Exposed Paddle Description, Table 6...................... 10

11/2008—Revision 0: Initial Version