LTC4216IDE datasheet(14/24 Pages) LINER

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LTC4216

4216f

Figure 8. Normal Power-Up/Power-Down Sequence

capacitors. A second timing cycle starts at time point 11

when the FB pin voltage exceeds 0.6V and the voltage

across the sense resistor drops below 25mV. ⎯R⎯E⎯S⎯E⎯T goes

high at the end of the second timing cycle (time point 12)

when TIMER reaches the VTMR(TH) threshold.

SENSEP

TIMER

GATE

VOUT

RESET

VCC

POWER GOOD

VFB > 0.6V

POWER BAD

VFB < 0.6V

(VGATE – VOUT) > VGS(TH)

VTMR(TH)

TRACKS SS RAMP

20µA

2µA

0.72V

0.4V

0.8V

10µA

1µA

5 6

7 8

CHECK FOR GATE,

FILTER, TIMER,

SS < 0.2V

CHECK FOR GATE, FILTER,

TIMER, SS < 0.2V AND FAULT HIGH

10 11 12

PLUG-IN CYCLE

FIRST TIMING CYCLE

POWER-GOOD DELAY

SECOND TIMING CYCLE

4216 F08

START

GATE

RAMP

ELECTRONIC CIRCUIT

BREAKER ARMED

RESET GOES HIGH

RESET

MODE

ON GOES LOW

RESET PULLED LOW

DUE TO POWER BAD

START 2ND TIMING CYCLE

(CHECK TIMER < 0.2V AND

FAULT HIGH)

APPLICATIO S I FOR ATIO

LTC4216IDE Datasheet(PDF) 14 Page - Linear Technology

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