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74FCT543ATSOG Datasheet(PDF) 3 Page - Integrated Device Technology

Part # 74FCT543ATSOG
Description  FAST CMOS OCTAL LATCHED TRANSCEIVER
PDF  7 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

74FCT543ATSOG Datasheet(HTML) 3 Page - Integrated Device Technology

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INDUSTRIALTEMPERATURERANGE
IDT74FCT543AT/CT
FASTCMOSOCTALLATCHEDTRANSCEIVER
3
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at TA = –55°C.
5. This parameter is guaranteed but not tested.
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VOH
Output HIGH Voltage
VCC = Min
IOH = –8mA
2.4
3.3
—
V
VIN = VIH or VIL
IOH = –15mA
2
3
—
VOL
Output LOW Voltage
VCC = Min
IOL = 64mA
—
0.3
0.55
V
VIN = VIH or VIL
IOS
Short Circuit Current
VCC = Max., VO = GND(3)
–60
–120
–225
mA
IOFF
Input/Output Power Off Leakage(5)
VCC = 0V, VIN or VO ≤
≤
≤
≤
≤
4.5V
—
—
±
1µ A
OU T PU T DRI V E CH ARACT ERI ST I CS
Symbol
Parameter
Test Conditions(1)
Min.
Typ.(2)
Max.
Unit
VIH
Input HIGH Level
Guaranteed Logic HIGH Level
2
—
—
V
VIL
Input LOW Level
Guaranteed Logic LOW Level
—
—
0.8
V
IIH
Input HIGH Current(4)
VCC = Max.
VI = 2.7V
—
—
±
1µ A
IIL
Input LOW Current(4)
VCC = Max.
VI = 0.5V
—
—
±
1µ A
IOZH
High Impedance Output Current
VCC = Max
VO = 2.7V
—
—
±
1µ A
IOZL
(3-State output pins)(4)
VO = 0.5V
—
—
±
1
II
Input HIGH Current(4)
VCC = Max., VI = VCC (Max.)
—
—
±
1µ A
VIK
Clamp Diode Voltage
VCC = Min, IIN = -18mA
—
–0.7
–1.2
V
VH
Input Hysteresis
—
—
200
—
mV
ICC
Quiescent Power Supply Current
VCC = Max., VIN = GND or VCC
—
0.01
1
mA
DC ELECT RI CAL CH ARACT ERI ST I CS OV ER OPERAT I N G RAN GE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, VCC = 5.0V ±5%
FU N CT I ON TABLE(1, 2)
For A-t o-B (Sym m e t ric w it h B-t o-A)
Latch
Output
Inputs
Status
Buffers
CEAB
LEAB
OEAB
A-to-B
B0–B7
H
X
X
Storing
High Z
X
H
X
Storing
X
X
X
H
X
High Z
L
L
L
Transparent
Current A Inputs
L
H
L
Storing
Previous* A Inputs
NOTES:
1. * Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
2. A-to-B data flow shown; B-to-A flow control is the same, except using CEBA, LEBA
and OEBA.



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