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LTC4441/LTC4441-1

44411f

APPLICATIO S I FOR ATIO

stability; the value of R2 can be varied to achieve the

required DRVCC voltage:

DRV

406

121

–.

The DRVCC regulator can supply up to 100mA and is short-

circuit protected. The output must be bypassed to the

PGND pin in very close proximity to the IC pins with a

minimum of 10µF ceramic, low ESR (X5R or X7R) capaci-

tor. Good bypassing is necessary as high transient supply

currents are required by the driver. If the input supply

voltage, VIN,is close to the required gate drive voltage, this

regulator can be disabled by connecting the DRVCC and FB

pins to VIN.

The LTC4441/LTC4441-1 monitors the FB pin for DRVCC’s

UVLO condition (UVLO in Figure 1). During power-up, the

driver output is held low until the DRVCC voltage reaches

90% of the programmed value. Thereafter, if the DRVCC

voltage drops more than 20% below the programmed

value, the driver output is forced low.

Logic Input Stage

The LTC4441/LTC4441-1 driver employs TTL/CMOS com-

patible input thresholds that allow a low voltage digital

1.09V

OUT

CVCC

4441 F01

1.21V

UVLO

DRIVER

ENABLE

DRIVER

MREG

330k

VIN

DRVCC

PGND

REG

LTC4441

Figure 1. DRVCC Regulator

signal to drive standard power MOSFETs. The LTC4441/

LTC4441-1 contains an internal voltage regulator that

biases the input buffer, allowing the input thresholds (VIH

= 2.4V, VIL = 1.4V) to be independent of the programmed

driver supply, DRVCC, or the input supply, VIN. The 1V

hysteresis between VIH and VIL eliminates false triggering

due to noise during switching transitions. However, care

should be taken to isolate this pin from any noise pickup,

especially in high frequency, high voltage applications.

The LTC4441/LTC4441-1 input buffer has high input

impedance and draws negligible input current, simplifying

the drive circuitry required for the input. This input can

withstand voltages up to 15V above and below ground.

This makes the chip more tolerant to ringing on the input

digital signal caused by parasitic inductance.

Driver Output Stage

A simplified version of the LTC4441/LTC4441-1’s driver

output stage is shown in Figure 2.

DRVCC

LTC4441

PGND

OUT

CGD

VIN

POWER

MOSFET

4441 F02

LOAD

INDUCTOR

CGS

Figure 2. Driver Output Stage

The pull-up device is the combination of an NPN transis-

tor, Q1, and a P-channel MOSFET, P1. This provides both

the ability to swing to rail (DRVCC) and deliver large peak

charging currents.

The pull-down device is an N-channel MOSFET, N1, with

a typical on resistance of 0.35Ω. The low impedance of N1

provides fast turn-off of the external power MOSFET and

holds the power MOSFET’s gate low when its drain voltage

switches. When the power MOSFET’s gate is pulled low

(gate shorted to source through N1) by the LTC4441/

LTC4441-1, its drain voltage is pulled high by its load (e.g.,

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