ES8396 datasheet(6/13 Pages) EVEREST

6 / 13 page

Everest Semiconductor

Confidential

ES8396

Revision 5.0

March 2018

4. CLOCK MODES AND SAMPLING FREQUENCIES

The device supports three types of clocking: standard audio clocks (256Fs, 384Fs, 512Fs, etc),

USB clocks (12/24 MHz), and an on-chip 22-bit fractional PLL clock.

According to the serial audio data sampling frequency (Fs), the device can work in two speed

modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges

from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.

The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and

SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the

system clock with specific rates. In master mode, LRCK and SCLK are derived internally from

device master clock.

5. MICRO-CONTROLLER CONFIGURATION INTERFACE

The device supports standard I2C micro-controller configuration interface. External micro-

controller can completely configure the device through writing to internal configuration

registers.

I2C interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line

(SCL) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1.

Data are transmitted synchronously to SCL clock on the SDA line on a byte-by-byte basis. Each

bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred

byte is followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of

this interface can be up to 100 kbps.

Figure 1 Data Transfer for I2C Interface

A master controller initiates the transmission by sending a “start” signal, which is defined as a

high-to-low transition at SDA while SCL is high. The first byte transferred is the slave address. It

is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x

equals AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is

received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by

the RW bit. The master can terminate the communication by generating a “stop” signal, which is

defined as a low-to-high transition at SDA while SCL is high.

ES8396 Datasheet(PDF) 6 Page - Suzhou Everest Semiconductor Co. Ltd.