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ES8396 Datasheet(PDF) 11 Page - Suzhou Everest Semiconductor Co. Ltd.

Part # ES8396
Description  Low Power Stereo Audio CODEC
PDF  13 Pages
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Manufacturer  EVEREST [Suzhou Everest Semiconductor Co. Ltd.]
Direct Link  http://www.everest-semi.com/en_index.html
Logo EVEREST - Suzhou Everest Semiconductor Co. Ltd.

ES8396 Datasheet(HTML) 11 Page - Suzhou Everest Semiconductor Co. Ltd.

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Everest Semiconductor
Confidential
ES8396
Revision 5.0
11
March 2018
LRCK duty cycle
40
60
%
SCLK frequency
26
MHz
SCLK pulse width low
TSCLKL
15
ns
SCLK Pulse width high
TSCLKH
15
ns
SCLK falling to LRCK edge
TSLR
–10
10
ns
SCLK falling to SDOUT valid
TSDO
0
ns
SDIN valid to SCLK rising setup time
TSDIS
10
ns
SCLK rising to SDIN hold time
TSDIH
10
ns
Figure 8 Serial Audio Port Timing
I2C SWITCHING SPECIFICATIONS
PARAMETER
Symbol
MIN
MAX
UNIT
SCL Clock Frequency
FSCL
400
KHz
Bus Free Time Between Transmissions
TTWID
1.3
us
Start Condition Hold Time
TTWSTH
0.6
us
Clock Low time
TTWCL
1.3
us
Clock High Time
TTWCH
0.4
us
Setup Time for Repeated Start Condition
TTWSTS
0.6
us
SDA Hold Time from SCL Falling
TTWDH
900
ns
SDA Setup time to SCL Rising
TTWDS
100
ns
Rise Time of SCL
TTWR
300
ns
Fall Time SCL
TTWF
300
ns



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