M032LE2AE datasheet(75/274 Pages) NUVOTON

75 / 274 page

M031/M032

Feb 25, 2019

Page 75 of 274

Rev. 1.01

FUNCTIONAL DESCRIPTION

6.1 Arm

® Cortex® -M0 Core

The Cortex

® -M0 processor is a configurable, multistage, 32-bit RISC processor, which has an

AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug

functionality. The processor can execute Thumb code and is compatible with other Cortex

® -M

profile processor. The profile supports two modes -Thread mode and Handler mode. Handler

mode is entered as a result of an exception. An exception return can only be issued in Handler

mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.

Figure 6.1-1 shows the functional controller of processor.

Cortex-M0

Processor

Core

Nested

Vectored

Interrupt

Controller

(NVIC)

Breakpoint

and

Watchpoint

Unit

Debugger

interface

Bus matrix

Debug

Access Port

(DAP)

Debug

Cortex-M0 Processor

Cortex-M0 Components

Wakeup

Interrupt

Controller

(WIC)

Interrupts

Serial Wire or

JTAG debug port

AHB-Lite interface

Figure 6.1-1 Functional Block Diagram

The implemented device provides:



A low gate count processor:

–

Arm

® 6-M Thumb® instruction set

–

Thumb-2 technology

–

Arm

® 6-M compliant 24-bit SysTick timer

–

A 32-bit hardware multiplier

–

System interface supported with little-endian data accesses

–

Ability to have deterministic, fixed-latency, interrupt handling

–

Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to

facilitate rapid interrupt handling

–

C Application Binary Interface compliant exception model. This is the Armv6-M, C

Application Binary Interface (C-ABI) compliant exception model that enables the use

of pure C functions as interrupt handlers

–

Low Power Sleep mode entry using the Wait For Interrupt (WFI), Wait For Event

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