M032LE2AE datasheet(13/274 Pages) NUVOTON

13 / 274 page

M031/M032

Feb 25, 2019

Page 13 of 274

Rev. 1.01



Programmable initial value



Supports programmable order reverse setting for input data

and CRC checksum



Supports programmable 1’s complement setting for input data

and CRC checksum.



Supports 8/16/32-bit of data width



Interrupt generated once checksum error occurs



Programmable seed value



8-bit write mode: 1-AHB clock cycle operation



16-bit write mode: 2-AHB clock cycle operation



32-bit write mode: 4-AHB clock cycle operation



Supports using PDMA to write data to perform CRC operation

Peripheral DMA (PDMA)



Supports up to 5 independent configurable channels for

automatic data transfer between memories and peripherals



Channel 0, 1 supports time-out function



Basic and Scatter-Gather Transfer modes



Each channel supports circular buffer management using

Scatter-Gather Transfer mode



Two types of priorities modes: Fixed-priority and Round-robin

modes



Transfer data width of 8, 16, and 32 bits



Single and burst transfer type



Source and destination address can be increment or fixed.



PDMA transfer count up to 65536



Request source can be from software, SPI/I

2S, USPI, UART,

UUART, I

2C, ADC, PWM and Timer

Clocks

External Clock Source



4~24 MHz High-speed eXternal crystal oscillator (HXT) for

precise timing operation



32.768 kHz Low-speed eXternal crystal oscillator (LXT) for RTC

function and low-power system operation



Supports clock failure detection for external crystal oscillators

and exception generatation (NMI)

Internal Clock Source



48 MHz High-speed Internal RC oscillator (HIRC) trimmed to

2% accuracy that can optionally be used as a system clock



38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog

timer and wakeup operation



Up to 96 MHz on-chip PLL, sourced from HIRC or HXT, allows

CPU operation up to the maximim CPU frequency without the

need for a high-frequency crystal

Timers

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