FS9701B datasheet(34/46 Pages) FORTUNE

34 / 46 page

FS970X

Rev. 4.4

34/46

ADG<7:6>

Performance setting of ADC

Section 8.7

SETADC<7:6> ENVDS & ENVCS, on/off power control setting

Section 5.3

SETADC<5:4> CYS<1:0> elimination mode setting of offset voltage of ADC

Section 8.5

SETADC<3:0> TPS1<1:0> and TPS2<1:0> the number of digital filter

Section 8.4

MISC1<7>

CNTBP and CMP1of ENBP and MISC2<3> determine the action

of buzzer

Chart 4

MISC1<6:3>

Setting of clock generator controls the operating mode of capacity

measurement

Chart 3, Chart 7

and Chart 8

MISC1<2:1>

DTON and FQRST_ are the counter mode of frequency counter

and reset control

Section 9.1

MISC1<0>

PKHRST_ is the reset signal of peak-hold sampling circuitry

Section 9.2

MISC2<6:4>

Output of compactor and low voltage detector

Section 7.5 and 5.1

MISC2<2>

When equal 1, the signal of CMPH can directly input from ACA,

without going through an AC buffer

Section 7.5.1

MISC2<1:0>

ENGNDR_ and ENLBS are the enable control of basic job offset

voltage and low voltage detector.

5.1 and 5.2

Chart

19. The brief illustration of the function of each register in FS970X.

The read/write sequence of each control register is shown as Graph 15. Because of the data length is 8 bit, it

requires consecutive two times for each read or write, first MSB, and then LSB（4 bits each）”0” when the next

ALE occurred. Thus, it will start with MSB again when starting the next read/write sequence.

ALE

RD_

CS_

Address, 00~08

DATA<7:4>

READ CONTROL REGISTER CYCLE

DATA<3:0>

AD<3:0>

ALE

WR_

CS_

Address, 00~08

DATA<7:4>

WRITE CONTROL REGISTER CYCLE

DATA<3:0>

Next Address

CYCNTR

AD<3:0>

Graph 15. The read/write sequence of the control register.

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