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IRMCF188TY Datasheet(PDF) 35 Page - International Rectifier |
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IRMCF188TY Datasheet(HTML) 35 Page - International Rectifier |
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35 / 38 page  IRMCF188 35 www.irf.com © 2014 International Rectifier March 10, 2017 Pin Number Pin Name Internal Pull- up /Pull-down Pin Type Description 33 ADCL I Input, Analog input channel dedicated for A/D compensation (0 – 1.2V), internally biased to 0.6V, see Figure 23 for internal structure 34 OP3- I Op amp negative input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused 35 OP3+ I Op amp positive input for application sensing, 0-1.2V range, needs to be pulled down to AVSS if unused 36 OP3O O Op amp output for application sensing, 0-1.2V range 37 AVSS P Analog common 38 VDDCAP P Internal 1.8V output, Capacitor(s) to be connected 39 VDD1 P 3.3V digital power 40 VSS P Digital common 41 P3.1/AOPWM2 I/O Discrete programmable I/O or PWM 2 digital output 42 PWMWL 58 kΩ Pull down O PWM gate drive for phase W low side, configurable either high or low true. 43 PWMVL 58 kΩ Pull down O PWM gate drive for phase V low side, configurable either high or low true 44 PWMUL 58 kΩ Pull down O PWM gate drive for phase U low side, configurable either high or low true 45 PWMWH 58 kΩ Pull down O PWM gate drive for phase W high side, configurable either high or low true 46 P3.7 I/O Discrete programmable I/O 47 P2.1 I/O Discrete programmable I/O 48 PWMVH 58 kΩ Pull down O PWM gate drive for phase V high side, configurable either high or low true 49 PWMUH 58 kΩ Pull down O PWM gate drive for phase U high side, configurable either high or low true 50 P1.5 I/O Discrete programmable I/O. 51 PFCPWM I/O PFC PWM gate drive , configurable either high or low 52 PFCGKILL 70 kΩ Pull up I PFCPWM shutdown input, active low input. 53 GATEKILL 70 kΩ Pull up I PWM shutdown input, configurable digital filter, active low input. 54 P3.0/INT2/CS1 70 kΩ Pull up I/O Discrete programmable I/O or external interrupt 2 input or SPI Chip Select 1 55 P5.2/TMS I JTAG test mode select or digital input port 56 TDO O JTAG test data output 57 P5.1/TDI I JTAG test data input or digital input port 58 TCK I JTAG test clock 59 RESET I Reset, low true, Schmitt trigger input 60 P1.1/RXD I/O UART receiver input or Discrete programmable I/O 61 P1.2/TXD I/O UART transmitter output or Discrete programmable I/O 62 P3.4/T0 I/O Discrete programmable I/O or Timer/Counter 2 input 63 P3.5/T1 I/O Discrete programmable I/O or Timer/Counter 2 input 64 P3.3/INT1 I/O Interrupt 1 input or Discrete I/O Table 22. Pin List |
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