NT5CC64M16GP-EKB datasheet(63/160 Pages) NANYA

63 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied. Depending on

the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands may be required to

compensate for the voltage and temperature drift as described in “ZQ Calibration Commands”. To issue ZQ calibration

commands, applicable timing requirements must be satisfied.

CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh re-entry.

Upon exit from Self-Refresh, the DDR3(L) SDRAM can be put back into Self-Refresh mode after waiting at least tXS period

and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be registered on each

positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during tXSDLL.

The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed when CKE is

raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3(L) SDRAM requires a minimum of one extra

refresh command before it is put back into Self-Refresh mode.

Self-Refresh Entry/Exit Timing

CK, CK

Ta0

Tb0

Tc0

Tc1

Te0

ODTL

tCKSRE

tCKSRX

tCPDED

tRP

SRE

NOP

Valid 2)

tCKESR

tXSDLL

tXS

CMD

ODT

Note:

1. Only NOP or DES commands

2. Valid commands not requiring a locked DLL

3. Valid commands requiring a locked DLL

Td0

Valid

CKE

NOP

SRX

NOP 1)

Valid 3)

Valid

Enter Self Refresh

Exit Self Refresh

Do Not

Care

Time

Break

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