NT5CC64M16GP-EKB datasheet(37/160 Pages) NANYA

37 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

DLL “off” to DLL “on” Procedure

To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh:

1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must

be in high impedance state before Self-Refresh mode is entered).

2. Enter Self Refresh Mode, wait until tCKSRE satisfied.

Change frequency, in guidance with “Input clock frequency change” section.

4. Wait until a stable is available for at least (tCKSRX) at DRAM inputs.

5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from subse-

quent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when Self

Refresh mode was entered. The ODT signal must continuously be registered LOW until tDLLK timings from subsequent

DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self Refresh mode was

entered, ODT signal can be registered LOW or HIGH.

Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.

Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.

8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be

necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during or

after tDLLK).

9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying

command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.

NT5CC64M16GP-EKB Datasheet(PDF) 37 Page - Nanya Technology Corporation.