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MSCPSI Datasheet(PDF) 5 Page - Mixed Signal Integration |
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MSCPSI Datasheet(HTML) 5 Page - Mixed Signal Integration |
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5 / 17 page ![]() Serial Control Register The MSCPSI uses serial data control with address and data clocked in with 21 cycles of the CLK clock. The data strobe (DS) resets the internal address data shift register. The address is a 4 bit nibble followed by a 16 bit word. Address Description 0000 Calibration Control Register; Controls signal on pin 18 0001 Offset DAC control level Controls volt age at pin 29; AAF and OpAmp current control Address Description 0010 Amp and Antialias filter1 and 2 control 0011 Highpass Filter Control Register 0100 Lowpass Filter Control Register 0101 A/D converter and Watchdog timer Control Register 0110 Watchdog Timer Count Register Controller Programmable Sensor Interface Preliminary Data Sheet 08/2006 © ©2 20 00 06 6 M Miixxeedd SSiiggnnaall IInntteeggrraattiioonn 5 5 W Weebb SSiittee ““w ww ww w..m miixx-ssiigg..ccoom m”” CLO CK 10 ns 10 ns NOMINAL NOMINAL DS A3 A2 A1 A0 D15D14D13D12D11D10D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3-A0/D 15-D0 FIGURE 2: TIMING DIAGRAM OF ADDRESS/DATA INPUT |
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