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GS3281 Datasheet(PDF) 65 Page - Semtech Corporation |
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GS3281 Datasheet(HTML) 65 Page - Semtech Corporation |
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65 / 97 page ![]() GS3281 Final Data Sheet Rev.7 PDS-061453 January 2019 65 of 97 Semtech Proprietary & Confidential www.semtech.com 0B PLL_LOOP_ BANDWIDTH_ 1 RSVD 15:13 R/W 0 Reserved - do not modify. CFG_PLL_LBW_3G 12:8 R/W 8 Configure PLL loop bandwidth in terms of ratio to nominal loop bandwidth 'x' (see Table 2-3). 2.97Gb/s (3G) loop bandwidth setting: 0x00 = Reserved - do not use 0x01 = 0.0625x 0x02 = 0.125x 0x03 = 0.1875x 0x04 = 0.25x 0x05 = 0.3125x 0x06 = 0.375x 0x07 = 0.4375x 0x08 = 0.5x 0x09 = 0.5625x 0x0A = 0.625x 0x0B = 0.6875x 0x0C = 0.75x 0x0D = 0.8125x 0x0E = 0.875x 0x0F = 0.9375x 0x10 to 0x1B = Reserved - do not use 0x1C = 1.0x (nominal) 0x1D = 1.0625x 0x1E = 1.125x 0x1F = 1.1875x RSVD 7:5 R/W 0 Reserved - do not modify. CFG_PLL_LBW_HD 4:0 R/W 8 Configure 1.485Gb/s (HD) PLL loop bandwidth in terms of ratio to nominal loop bandwidth 'x' (see Table 2-3). See CFG_PLL_LBW_3G parameter for available settings. 0C PLL_LOOP_ BANDWIDTH_ 2 RSVD 15:13 R/W 0 Reserved - do not modify. CFG_PLL_LBW_SD 12:8 R/W 1C Configure 270Mb/s (SD) PLL loop bandwidth in terms of ratio to nominal loop bandwidth 'x' (see Table 2-3). See CFG_PLL_LBW_3G parameter for available settings. RSVD 7:5 R/W 0 Reserved - do not modify. CFG_PLL_LBW_MADI 4:0 R/W 8 Configure 125Mb/s (MADI) PLL loop bandwidth in terms of ratio to nominal loop bandwidth 'x' (see Table 2-3). See CFG_PLL_LBW_3G parameter for available settings. 0D RSVD RSVD 15:0 R/W 8 Reserved - do not modify. 0E to 0F RSVD RSVD 15:0 R/W 0 Reserved - do not modify. Table 5-3: Control Register Descriptions (Continued) Addressh Register Name Parameter Name Bit Slice R/W Reset Valueh Description |
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