ICL7107SCPL datasheet(10/17 Pages) ARTSCHIP

10 / 17 page

ICL7106,ICL7107,ICL7016S,ISL7107S

31/2 Digit,

LCD/LED Display, A/D Converters

www.artschip.com

FIGURE 8. ICL7107 DIGITAL SECTION

System Timing

Figure 9 shows the clocking arrangement used in the ICL7106

and ICL7107. Two basic clocking arrangements can be used:

Figure 9A. An external oscillator connected to pin 40.

Figure 9B. An R-C oscillator using all three pins.

The oscillator frequency is divided by four before it clocks the

decade counters. It is then further divided to form the three

convert-cycle phases. These are signal integrate (1000

counts), reference de-integrate (0 to 2000 counts) and

auto-zero (1000 to 3000 counts). For signals less than full

scale, auto-zero gets the unused portion of reference

de-integrate. This makes a complete measure cycle of 4,000

counts (16,000 clock pulses) independent of input voltage.

For three readings/second, an oscillator frequency of 48kHz

would be used.

To achieve maximum rejection of 60Hz pickup, the signal

integrate cycle should be a multiple of 60 Hz. Oscillator

frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz,

1/3kHz, etc. should be selected. For 50Hz rejection,

Oscillator frequencies of 200kHz, 100kHz, 66

2/3kHz,

50kHz,40kHz, etc. would be suitable. Note that 40kHz (2.5

readings/second) will reject both 50Hz and 60Hz (also 400Hz

and 440Hz).

FIGURE 9B.

FIGURE 9. CLOCK CIRCUITS

ICL7107SCPL Datasheet(PDF) 10 Page - ARTSCHIP ELECTRONICS CO.,LMITED.