SC4810EITSTRT datasheet(10/24 Pages) SEMTECH

10 / 24 page

 2004 Semtech Corp.

www.semtech.com

SC4810A/B/C/D/E

POWER MANAGEMENT

Application Information (Cont.)

up so that the total power loss is less. D19, R59, C37,

T5, C36, D15 and R53 construct the driving circuit for

the auxiliary reset switch M15. The secondary side bias

circuit composed of R50, D13 and C38 is regulated to

about 7.5V via a linear regulator composed of R57, Q7

D16 and C39. The feedback of the converter is composed

of U10 (SC431), U11, R73, C47, C45, R72, R76, R70

and C46.

SC4810 is the PWM controller which processes the

voltage feedback plus current signal and generates

driving signals to drive the main switch and auxiliary reset

switch. SC1302A is a dual driver IC which is capable of

sourcing 3A peak current. To obtain the best performance,

SC1302A is adopted to drive M17 and M15 in the

Semtech application circuits. SC4810 features dual

complementary driving signals. And SC4810 also provides

adjustable leading-edge delay time for the driving signals,

which helps to achieve zero-voltage switching in active

clamp forward converter. R75 and R79 are the two

resistors available to adjust the delay for the

complementary driving. C50 is the soft-start capacitor.

R61 and R65 construct the voltage divider for the line

under voltage lock out protection. R64 and C44 construct

the circuit for the programmable power transformer

voltage-second production protection limits. This special

protection function provide the voltage-second balance

for the power transformer under different input line

conditions. R78 and R74 also provide an extra maximum

duty cycle protection for the power converter.

The clock signal is generated by C49 and R77. When VDD

of SC4810 hits the threshold voltage, VREF jumps up to

5.0V. VREF charges C49 via R77. C49 will be discharged

via an internal FET whenever the voltage on C49 reaches

3.0V. The selection of C49 and R77 is described in the

“Set Clock Frequency” section on the following page. Q9

works as a buffer between the clock signal and the slope

compensation signal to minimize the interference on the

system clock signal. R80 is a pull-up resistor tied to VREF.

Since SYNC function is not utilized, SYNC pin is grounded

via R71.

Power Transformer Design

A power transformer with the turns ration of 6 to 1 was

designed for this application. With the turns ratio of 6:1,

the duty ratio under different input line and load conditions

were calculated to verify feasibility.

A self-driven configuration was adopted on the secondary

side for driving the synchronous rectification FETs. One

extra winding (Pin8~Pin9) was added at the bottom side

of the power transformer’s secondary side to drive the

freewheeling FET. The forward FET was driven directly

from the top of the power winding. Primary side auxiliary

winding was used to generated primary side bias to

improve the converter’s efficiency.

The final configuration of the power transformer is

illustrated as Fig. 2.

6T(PRI)

2T(PRI AUX)

1T(SEC)

1T(SEC AUX)

1T(SEC)

Fig.2 Illustration of the power transformer

PA0576 (PUSLE ENGINEERING)

For detailed information about PA0576, please check the

appendix on page 17.

Power MOSFET Selection

The selection of the switching power MOSFET is based

on the peak & RMS current rating, the total gate charge,

Rds and drain to source voltage rating. In this application,

SI4842 was chosen for the secondary side synchronous

rectification MOSFET. And SI4488 was chosen for the

primary side main switching and reset MOSFET.

Output Filter Design

The output filtering circuit consists of the output inductor

and output capacitors. The design of the output capacitor

usually depends on the specification of the requirement

of the output ripple. Given the worst case output ripple

requirement and peak to peak output current ripple plus

the duty ratio under the different line and load condition,

output capacitance is calculated to meet the output ripple

requirement. After all, ESR and ESL of the output

capacitor under certain switching frequency should also

be considered during the calculation. The value of the

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