SC4810EITSTRT datasheet(12/24 Pages) SEMTECH

12 / 24 page

 2004 Semtech Corp.

www.semtech.com

SC4810A/B/C/D/E

POWER MANAGEMENT

Application Information (Cont.)

Clock Signal of SC4810

DMAX

Fig. 5 Illustration for DMAX

VRCT

VDMAX

In this application, V

DMAX was designed to be 2.8V. So the

MAX = 90%.

Limit for Power Transformer

Voltage Second Product

The SC4810 also features programmable limits for power

transformer voltage-second product. As illustrated in Fig.

6 and Fig. 7 RAMP pin is charged up via a resistor R from

the input line voltage. The capacitor C will be discharged

via an internal FET shorted to ground and the output

OUT1 will be pulled low whenever the voltage on RAMP

pin hits 3V. By adjusting the values of the resistor R and

the value of the capacitor C, the maximum voltage-sec-

ond product imposed on the power transformer is pre-

set. The maximum voltage-second product limitation helps

prevent saturation of the power transformer.

Voltage waveform on RAMP pin

Maximum OUT1 of SC4810

Fig. 6 Illustration of the programmable limits for power

transformer voltage-second product

VRAMP

OUT1

RAMP

Fig. 7 Illustration for Maximum voltage-

second product on the power transformer

The selection of the R and C should consider the maxi-

mum voltage rating of the main switching FET. In this

application, the voltage rating of SI4488 is 150V. Since

Vin*D/(1-D) = 150V, D = 0.8 for low line 36V. So to get

80% at low line, R = 165kOhms and C = 220pF were

selected using volt-second product equation:

3 • Ramp • Cramp.

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