D17133CS datasheet(46/289 Pages) NEC

46 / 289 page

CHAPTER 5 DATA MEMORY (RAM)

Data memory stores data such as operation and control data. Data can be read from or written to data memory

with an instruction during normal operation.

5.1 DATA MEMORY CONFIGURATION

Figure 5-1 shows the configuration of data memory.

Data memory is controlled by the concept called banks. The

µPD17120 subseries has BANK0 only.

An address is allocated to the data memory for each bank.

An address consists of four bits of memory called "a nibble".

The address of data memory consists of 7 bits. The three high-order bits are called "the row address", and the

four low-order bits are called "the column address". For example, when the address of data memory is 1AH

(0011010B), the row address is 1H (001B), and the column address is AH (1010B).

In the case of the

µPD17120 and 17121, addresses 40H to 6EH should not be used because they are non-mounted

areas.

Sections 5.1.1 to 5.1.6 describe functions of data memory other than its use as address space.

Figure 5-1. Configuration of Data Memory

0123456789

DBF3 DBF2 DBF1 DBF0

P0E

(2 bits)

P0A

4 bits

P0B

4 bits

P0C

4 bits

P0D

4 bits

System register

Example:

Address 1AH

of BANK0

BANK0

Remark

The shaded parts represent the non-mounted area in the case of the

µPD17120 and 17121.

D17133CS Datasheet(PDF) 46 Page - NEC