NMOS linear image sensor

S3901/S3904 series

s Driver circuit

S3901/S3904 series do not require any DC voltage supply

for operation. However, the Vss, Vsub and all NC terminals

must be grounded. A start pulse

φst and 2-phase clock pulses

φ1, φ2 are needed to drive the shift register. These start and

clock pulses are positive going pulses and CMOS logic com-

patible.

The 2-phase clock pulses

φ1, φ2 can be either completely

separated or complementary. However, both pulses must not

be “High” at the same time.

A clock pulse space (X1 and X2 in Figure 7) of a “rise time/fall

time - 20” ns or more should be input if the rise and fall times

of

φ1, φ2 are longer than 20 ns. The φ1 and φ2 clock pulses

must be held at “High” at least 200 ns. Since the photodiode

signal is obtained at the rise of each

φ2 pulse, the clock pulse

frequency will equal the video data rate.

The amplitude of start pulse

φst is the same as the φ1 and φ2

pulses. The shift register starts the scanning at the “High”

level of

φst, so the start pulse interval determines the length of

signal accumulation time. The

φst pulse must be held “High”

at least 200 ns and overlap with

φ2 at least for 200 ns. To

operate the shift register correctly,

φ2 must change from the

“High” level to the “Low” level only once during “High” level of

φst. The timing chart for each pulse is shown in Figure 7.

s End of scan

The end of scan (EOS) signal appears in synchronization

with the

φ2 timing right after the last photodiode is addressed,

and the EOS terminal should be pulled up at 5 V using a 10

k

Ω resistor.

tvd

tpw 1

tpw 2

tpw s

st

V s (H)

V s (L)

V 1 (H)

V 1 (L)

V 2 (H)

V 2 (L)

1

2

END OF SCAN

st

1

2

tr s

tf s

tr 1

tf 1

X1

X2

t ov

tf 2

tr 2

ACTIVE VIDEO OUTPUT

KMPDC0022EA

Figure 7 Timing chart for driver circuit

s Signal readout circuit

There are two methods for reading out the signal from an NMOS

linear image sensor. One is a current detection method using

the load resistance and the other is a current integration method

using a charge amplifier. In either readout method, a positive

bias must be applied to the video line because photodiode

anodes of NMOS linear image sensors are set at 0 V (Vss).

Figure 8 shows a typical video bias voltage margin. As the clock

pulse amplitude is higher, the video bias voltage can be set

larger so the saturation charge can be increased. The rise and

fall times of the video output waveform can be shortened if the

video bias voltage is reduced while the clock pulse amplitude is

still higher. When the amplitude of

φ1, φ2 and φst is 5 V, setting

the video bias voltage at 2 V is recommended.

To obtain good linearity, using the current integration method is

advised. In this method, the integration capacitance is reset to

the reference voltage level immediately before each photodiode

is addressed and the signal charge is then stored as an integra-

tion capacitive charge when the address switch turns on. Fig-

ures 9 and 10 show a typical current integration circuit and its

pulse timing chart. To ensure stable output, the rise of a reset

pulse must be delayed at least 50 ns from the fall of

φ2.

Hamamatsu provides the following driver circuits and related

products (sold separately).

KMPDB0043EA

Figure 8 Video bias voltage margin

4

0

6

8

10

4

567

8

10

CLOCK PULSE AMPLITUDE (V)

2

9

MIN.

VIDEO BIAS RANGE

MAX.

RECOMMENDED

BIAS

Product

name

Type No.

Content

Feature

C7883

High-speed

driver circuit

C7883G

C7883

+ C8225-01

High-speed operation

Single power supply

(+15 V) operation

Compact

C7884

Precision

driver circuit

C7884G

C7884

+ C8225-01

Low noise

Good output linearity

Boxcar waveform output

C7884-01

High precision

driver circuit

Driver

circuit

C7884G-01

C7884-01

+ C8225-01

Ultra-low noise

Good output linearity

Boxcar waveform output

Pulse

generator C8225-01

C7883,

C7884 series

Cable

A8226

C7883 to

C7885 series BNC, length 1 m