AMC1336DWVR datasheet(8/31 Pages) TI1

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AMC1336

SBAS951 – AUGUST 2019

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Electrical Characteristics (continued)

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V,

AINP = –1 V to +1 V, and AINN = AGND = 0 V; typical specifications are at TA = 25°C, AVDD = 5 V, DVDD = 3.3 V, and

fCLKIN = 20 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(2)

Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer

function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.

(3)

Offset error drift is calculated using the box method, as described by the following equation: TCEO = (valueMAX – valueMIN) /

TempRange.

(4)

Gain error drift is calculated using the box method, as described by the following equation: TCEG (ppm) = ((valueMAX – valueMIN) / (value

× TempRange)) × 106.

DC ACCURACY

Resolution

Decimation filter output set to 16 bits

Bit

INL

Integral nonlinearity(2)

Resolution: 16 bits

–12

±2

LSB

Offset error

Initial, at TA = 25°C, AINP = AINN = AGND

–0.5

±0.03

0.5

TCEO

Offset error thermal drift(3)

–6

±0.1

µV/°C

CMRR

Common-mode rejection

ratio

fIN = 0 Hz, VCM min ≤ VCM ≤ VCM max

–104

fIN = 10 kHz, VCM min ≤ VCM ≤ VCM max

–88

PSRR

Power-supply rejection ratio

PSRR vs AVDD, at DC

–90

PSRR vs AVDD, 100-mV and 10-kHz ripple

–84

Gain error(1)

Initial, at TA = 25°C, VAINP = 1 V or VAINN = –1

V, AINN = AGND

–0.25%

±0.02%

0.25%

TCEG

Gain error drift(4)

–45

±20

ppm/°C

AC ACCURACY

SNR

Signal-to-noise ratio

VIN = 2 VPP, fIN = 1 kHz

SINAD

Signal-to-noise + distortion

VIN = 2 VPP, fIN = 1 kHz

THD

Total harmonic distortion

VIN = 2 VPP, fIN = 1 kHz

–87

–78

SFDR

Spurious-free dynamic range

VIN = 2 VPP, fIN = 1 kHz

DIGITAL INPUT (CMOS Logic With a Schmitt Trigger)

IIN

Input current

DGND

≤ VIN ≤ DVDD

µA

CIN

Input capacitance

VIH

High-level input voltage

0.7 x DVDD

DVDD + 0.3

VIL

Low-level input voltage

–0.3

0.3 x DVDD

DIGITAL OUTPUT (CMOS)

CLOAD

Output load capacitance

fCLKIN = 21 MHz

VOH

High-level output voltage

IOH = –20 µA

DVDD – 0.1

IOH = –4 mA

DVDD – 0.4

VOL

Low-level output voltage

IOL = 20 µA

0.1

IOL = 4 mA

0.4

POWER SUPPLY

AVDDPOR

AVDD power-on reset

threshold voltage

AVDD falling

1.75

2.15

2.7

IAVDD

High-side supply current

3 V

≤ AVDD ≤ 3.6 V

6.5

4.5 V

≤ AVDD ≤ 5.5 V

7.5

IDVDD

Controller-side supply current

2.7 V

≤ DVDD ≤ 3.6 V, CLOAD = 15 pF

3.5

4.5 V

≤ DVDD ≤ 5.5 V, CLOAD = 15 pF

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