LM2696MXAX datasheet(15/19 Pages) NSC

15 / 19 page

Application Information (Continued)

LINE REGULATION

The LM2696 regulates to the lowest point of the output

voltage (V

L in Figure 8 ). This is to say that the output voltage

may be represented by a waveform that is some average

voltage with ripple. The LM2696 will regulate to the trough of

the ripple.

The output voltage is given by the following relationship:

as discussed in the Feedback Resistor section of this docu-

ment.

TRANSIENT RESPONSE

Constant on-time architectures have inherently excellent

transient line and load response. This is because the control

loop is extremely fast. Any change in the line or load condi-

tions will result in a nearly instantaneous response in the

PWM off time.

If one considers the switcher response to be nearly cycle-

by-cycle, and amount of energy contained in a single PWM

pulse, there will be very little change in the output for a given

change in the line or load.

EFFICIENCY

The constant on-time architecture features high efficiency

even at light loads. The ability to achieve high efficiency at

light loads is due to the fact that the off-time will become

necessarily long at light loads. Having extended the off-time,

there is little mechanism for loss during this interval.

The efficiency is easily estimated using the following rela-

tionships:

Power loss due to FET:

FET =PC +PGC +PSW

Where:

C =D • (IOUT

2 • R

DS_ON)

GC =AVIN +VGS • QGS • fSW

SW = 0.5 • VIN ·IOUT • (tr +tf) • fSW

Typical values are:

DS_ON = 130 m

Ω

GS =4V

GS = 13.3 nC

r = 3.8 ns

f = 4.5 ns

Power loss due to catch diode:

D = (1-D) • (IOUT • Vf)

Power loss due to DCR and ESR:

DCR =IOUT

2 • R

DCR

ESR_OUTPUT =IRIPPLE

√12 • R

ESR_OUTPUT

ESR_INPUT =IOUT

2(D(1-D)) • R

ESR_INPUT

Power loss due to Controller:

CONT =VIN • IQ

Q is typically 1.3 mA

The efficiency may be calculated as shown below:

Total power loss = P

FET +PD +PDCR +PESR_OUTPUT +

ESR_INPUT +PCONT

Power Out = I

OUT • VOUT

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FIGURE 7. Parasitic Tank Circuit at the Switchpin

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FIGURE 8. Average Output Voltage and Regulation Point

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