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STR720 Datasheet(PDF) 145 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 145 Page - STMicroelectronics |
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145 / 401 page  STR720 - RESET AND CLOCK CONTROL UNIT (RCCU) 145/401 DIViders CONFiguration register (DIVCONF) Address Offset: 04h Reset value: 001Fh This register is write protected and can be unlocked using REG_PROT bit in SYSPROT register. Bit 15:5 = Reserved. Give ‘0’ when read and must be written to ‘0’. Bit 4:3 = Reserved. Bit 2 = ATAPI_SEL: ATAPI clock select 0: select AHB_CLK/2 as ATAPI clock 1: select AHB_CLK/3 as ATAPI clock Bit 1:0 = APB_DIV[1:0]: APB output clock divider factor. This bit field configures the A-APB clock generation. Refer to Table 38 for A-APB divider settings. 15 14 13 12 11 10 9 8 765432 1 0 Reserved Reserved ATAPI_ SEL APB_DIV[1:0] -rw rw rw rw rw Table 38. APB divider settings APB_DIV1 APB_DIV0 APB_CK 0 0 AHB_CLK/2 0 1 AHB_CLK/4 1 0 AHB_CLK/8 1 1 AHB_CLK/16 1 |
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