STR720 datasheet(146/401 Pages) STMICROELECTRONICS

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STR720 - RESET AND CLOCK CONTROL UNIT (RCCU)

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CLocK FLAG register (CLKFLAG)

Address Offset: 08h

Reset value: 0020h after Hardware reset

Reset value: 0021h after Software reset

Reset value: 0022h after Watchdog reset

Bit 15 = LOCK_I: lock changing interrupt bit

This bit indicates a 0 to 1 transition on the PLL LOCK signal. Only RCCU block can set it to ‘1’

when PLL reaches the lock condition. Application software writing ‘1’ on this bit will clear its

value; writing ‘0’ has no effect.

0: No lock interrupt request is provided

1: lock interrupt request is active

Bit 14 = ULOCK_I: unlock changing interrupt bit

This bit indicates a 1 to 0 transition on the PLL LOCK signal. Only RCCU block can set it to ‘1’

when PLL loses the lock condition. Application software writing ‘1’ on this bit will clear its

value; writing ‘0’ has no effect.

0: No unlock interrupt request is provided

1: unlock interrupt request is active

Bit 13:7 = Reserved. Give ‘0’ when read and must be written to ‘0’.

Bit 6 = DIV2_F: DIV2 mux status flag

This bit is read only. It indicates the actual status of the PLLCLKREF clock

0: indicates that PLLCLKREF is CLK

1: indicates that PLLCLKREF is CLK/2

Bit 5 = PLLBYP_F: PLL mux status flag

This bit is read only. It indicates that the PLLCLK clock is actually selected.

0: indicates that PLLCLK is selected

1: indicates that PLLCLK is not selected

Bit 4 = IDLE_F: IDLE mux status flag

This bit is read only. It indicates that the IDLE clock (PLLCLKREF/32) is actually selected.

0: indicates that IDLE clock is not selected

1: indicates that IDLE clock is selected

Bit 3 = SLOW_F: SLOW mux status flag

This bit is read only. It indicates that the CLK_AF clock is actually selected.

0: indicates that CLK_AF clock is not selected

1: indicates that CLK_AF clock is selected

765432

LOCK_I

ULOCK

Reserved

DIV2_F

PLLBY

P_F

IDLE_F

SLOW_

Res.

WDGR

ST_F

SWRST

rrrr-

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