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STR720 Datasheet(PDF) 148 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 148 Page - STMicroelectronics |
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148 / 401 page  STR720 - RESET AND CLOCK CONTROL UNIT (RCCU) 148/401 MaSK ConTroL register (MSKCTL) Address Offset: 10h Reset value: 0000h Bit 15 = LOCK_I_EN: Lock interrupt masking bit 0: No interrupt requests on PLL LOCK are provided by RCCU 1: The RCCU can request a LOCK interrupt Bit 14 = ULOCK_I_EN: UnLock interrupt masking bit 0: No interrupt requests on PLL UnLOCK are provided by RCCU 1: The RCCU can request a UnLOCK interrupt Bit 13:1 = Reserved. Give ‘0’ when read and must be written to ‘0’. Bit 0 = STOP_EN: STOP mode enable bit 0: STOP mode is not enabled. 1: STOP mode enabled. SYStem PROTection register (SYSPROT) Address Offset: 14h Reset value: 0000h Bit 15:1 = Reserved. Give ‘0’ when read and must be written to ‘0’. Bit 0 = REG_PROT: Register write protection bit This bit is set and cleared by software. It is cleared by hardware after every write access to PLLCONF, DIVCONF and CLKCTL registers. This bit enables the PLLCONF, DIVCONF and CLKCTL registers writing. 0: write access to PLLCONF, DIVCONF and CLKCTL registers is disabled 1: write access to PLLCONF, DIVCONF and CLKCTL registers is enabled 15 14 13 12 11 10 9 8 765432 1 0 LOCK_I _EN ULOCK _I_EN Reserved STOP_ EN rw rw - rw 15 14 13 12 11 10 9 8 765432 1 0 Reserved REG_P ROT -rw 1 |
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