TMS29F010

131072 BY 8-BIT

FLASH MEMORY

SMJS840A – NOVEMBER 1997 – REVISED JUNE 1998

18

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

IOL

IOH

Output

Under

Test

0.5 mA

– 0.5 mA

1.50 V

CL

(see Note A, Note B, and Note C)

2.4 V

0.45 V

2 V

0.8 V

VOLTAGE WAVEFORMS FOR -90, -10, -12

Conditions:

VIH = 2.4 V

VIL = 0.45 V

CL = 100 pF

Measurements taken at: 2.0 V for logic high

0.8 V for logic low

Input rise and fall = <20 ns

2 V

0.8 V

3.0 V

0.0 V

VOLTAGE WAVEFORMS FOR -70

1.5 V

Measurements taken at: 1.5 V for logic high

1.5 V for logic low

Input rise and fall = <5 ns

Conditions:

VIH = 3.0 V

VIL = 0.0 V

CL = 30 pF

1.5 V

NOTES: A. CL includes probe and fixture capacitance.

B. The ac testing inputs for -70 voltage waveforms are driven at 3 V for logic high and 0 V for logic low. Timing measurements for -70

voltage waveforms are made at 1.5 V for logic high and 1.5 V for logic low on both inputs and outputs. The ac testing inputs for -90,

-10, and -12 voltage waveforms are driven at 2.4 V for logic high and 0.45 V for logic low. Timing measurements for -90, -10, and

-12 voltage waveforms are made at 2 V for logic high and 0.8 V for logic low on both inputs and outputs.

C. Each device should have a 0.1-

µF ceramic capacitor connected between VCC and VSS, as closely as possible to the device pins.

Figure 1. AC Test Output Load Circuit and Voltage Waveforms