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STM32H742AI Datasheet(PDF) 168 Page - STMicroelectronics |
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STM32H742AI Datasheet(HTML) 168 Page - STMicroelectronics |
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168 / 357 page ![]() Electrical characteristics (rev Y) STM32H742xI/G STM32H743xI/G 168/357 DS12110 Rev 7 Figure 38. Quad-SPI timing diagram - SDR mode Figure 39. Quad-SPI timing diagram - DDR mode Table 85. QUADSPI characteristics in DDR mode(1) Symbol Parameter Conditions Min Typ Max Unit Fck1/t(CK) QUADSPI clock frequency 2.7 V<VDD<3.6 V CL=20 pF -- 100 MHz 1.62 V<VDD<3.6 V CL=15 pF -- 100 tw(CKH) QUADSPI clock high and low time - TCK/2 –0.5 - TCK/2 ns tw(CKL) TCK/2 - TCK/2+0.5 tsr(IN), tsf(IN) Data input setup time - 2 - - thr(IN), thf(IN) Data input hold time - 2 - - tvr(OUT), tvf(OUT) Data output valid time DHHC=0 - 3.5 4 DHHC=1 Pres=1, 2... -TCK/4+3.5 TCK/4+4 thr(OUT), thf(OUT) Data output hold time DHHC=0 3 - - DHHC=1 Pres=1, 2... TCK/4+3 - - 1. Guaranteed by characterization results. MSv36878V1 Data output D0 D1 D2 Clock Data input D0 D1 D2 t(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) ts(IN) th(IN) tv(OUT) th(OUT) MSv36879V1 Data output D0 D2 D4 Clock Data input D0 D2 D4 t(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) tsf(IN) thf(IN) tvf(OUT) thr(OUT) D1 D3 D5 D1 D3 D5 tvr(OUT) thf(OUT) tsr(IN) thr(IN) |
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