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STM32H742AI Datasheet(PDF) 278 Page - STMicroelectronics |
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STM32H742AI Datasheet(HTML) 278 Page - STMicroelectronics |
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278 / 357 page ![]() Electrical characteristics (rev V) STM32H742xI/G STM32H743xI/G 278/357 DS12110 Rev 7 Figure 90. Quad-SPI timing diagram - SDR mode Figure 91. Quad-SPI timing diagram - DDR mode 7.3.19 Delay block (DLYB) characteristics Unless otherwise specified, the parameters given in Table 183 for Delay Block are derived from tests performed under the ambient temperature, frcc_c_ck frequency and VDD supply voltage summarized in Table 122: General operating conditions, with the following configuration: MSv36878V1 Data output D0 D1 D2 Clock Data input D0 D1 D2 t(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) ts(IN) th(IN) tv(OUT) th(OUT) MSv36879V1 Data output D0 D2 D4 Clock Data input D0 D2 D4 t(CK) tw(CKH) tw(CKL) tr(CK) tf(CK) tsf(IN) thf(IN) tvf(OUT) thr(OUT) D1 D3 D5 D1 D3 D5 tvr(OUT) thf(OUT) tsr(IN) thr(IN) Table 183. Delay Block characteristics Symbol Parameter Conditions Min Typ Max Unit tinit Initial delay - 1400 2200 2400 ps t∆ Unit Delay - 35 40 45 - |
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