Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

STM32H742AI Datasheet(PDF) 307 Page - STMicroelectronics

Part # STM32H742AI
Description  32-bit Arm® Cortex®-M7 480MHz MCUs, up to 2MB Flash, up to 1MB RAM, 46 com. and analog interfaces
PDF  357 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H742AI Datasheet(HTML) 307 Page - STMicroelectronics

Back Button STM32H742AI Datasheet HTML 303Page - STMicroelectronics STM32H742AI Datasheet HTML 304Page - STMicroelectronics STM32H742AI Datasheet HTML 305Page - STMicroelectronics STM32H742AI Datasheet HTML 306Page - STMicroelectronics STM32H742AI Datasheet HTML 307Page - STMicroelectronics STM32H742AI Datasheet HTML 308Page - STMicroelectronics STM32H742AI Datasheet HTML 309Page - STMicroelectronics STM32H742AI Datasheet HTML 310Page - STMicroelectronics STM32H742AI Datasheet HTML 311Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 307 / 357 page
background image
DS12110 Rev 7
307/357
STM32H742xI/G STM32H743xI/G
Electrical characteristics (rev V)
322
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 205 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 122: General operating conditions, with the following
configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load CL = 30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS1
Refer to Section 7.3.15: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 205. SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SPI clock frequency
Master mode
1.62<VDD<3.6 V
SPI1, 2, 3
--
80
MHz
Master mode
2.7<VDD<3.6 V
SPI1, 2, 3
100
Master mode
1.62<VDD<3.6 V
SPI4, 5, 6
50
Slave receiver mode
1.62<VDD<3.6 V
100
Slave mode transmitter/full duplex
2.7<VDD<3.6 V
31
Slave mode transmitter/full duplex
1.62 <VDD<3.6 V
29
tsu(NSS)
NSS setup time
Slave mode
2
-
-
-
th(NSS)
NSS hold time
Slave mode
1
-
-
tw(SCKH),
tw(SCKL)
SCK high and low time
Master mode
TPCLK-2 TPCLK TPCLK+2



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com