 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DM368ZCEZ Datasheet(PDF) 28 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
DM368ZCEZ Datasheet(HTML) 28 Page - Texas Instruments |
|
|
28 / 208 page  TMS320DM368 SPRS668C – APRIL 2010 – REVISED JUNE 2011 www.ti.com Table 2-5. Pin Descriptions (continued) Name BGA Type Group Power IPU Reset Description(4) ID (1) Supply(2) IPD(3) State VSSA18_DAC E11 GND Video Video DAC: Analog 1.8-V ground DAC Note: If the DAC peripheral is not used, this pin must be tied directly to VSS for proper device operation. VSSA12_DAC F11 GND Video Video DAC: Analog 1.2-V ground DAC Note: If the DAC peripheral is not used, this pin must be tied directly to VSS for proper device operation. DDR_CLK W11 O DDR VDD18_DDR DDR Data Clock DDR_CLK W12 O DDR VDD18_DDR DDR Complementary Data Clock DDR_RAS U12 O DDR VDD18_DDR DDR Row Address Strobe DDR_CAS V12 O DDR VDD18_DDR DDR Column Address Strobe DDR_WE W13 O DDR VDD18_DDR DDR Write Enable DDR_CS T12 O DDR VDD18_DDR DDR Chip Select DDR_CKE R13 O DDR VDD18_DDR DDR Clock Enable DDR_DQM[1] W6 O DDR VDD18_DDR Data mask input for DDR_DQ[15:8] DDR_DQM[0] T11 O DDR VDD18_DDR Data mask input for DDR_DQ[7:0] DDR_DQS[1] T7 I/O DDR VDD18_DDR Data strobe input/outputs for each byte of the 16-bit data bus used to synchronize the data transfers. Output to DDR2 when writing and inputs when reading. They are used to synchronize the data transfers. DDR_DQS1: For DDR_DQ[15:8] DDR_DQS[0] T10 I/O DDR VDD18_DDR Data strobe input/outputs for each byte of the 16-bit data bus used to synchronize the data transfers. Output to DDR2 when writing and inputs when reading. They are used to synchronize the data transfers. DDR_DQS0: For DDR_DQ[7:0] DDR_DQSN[1] U6 I/O DDR VDD18_DDR DDR: Complimentary data strobe input/outputs for each byte of the 16-bit data bus. They are outputs to the DDR2 when writing and inputs when reading. They are used to synchronize the data transfers. Note: This signal is used in double ended differential memory interfaces supported by the device. DDR_DQSN[0] U9 I/O DDR VDD18_DDR DDR: Complimentary data strobe input/outputs for each byte of the 16-bit data bus. They are outputs to the DDR2 when writing and inputs when reading. They are used to synchronize the data transfers. Note: This signal is used in double ended differential memory interfaces supported by the device. DDR_BA[2] V13 O DDR VDD18_DDR Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[1] T13 O DDR VDD18_DDR Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_BA[0] W14 O DDR VDD18_DDR Bank select outputs. Two are required for 1Gb DDR2 memories. DDR_A13 T16 O DDR VDD18_DDR DDR Address Bus bit 13 DDR_A12 V17 O DDR VDD18_DDR DDR Address Bus bit 12 DDR_A11 W18 O DDR VDD18_DDR DDR Address Bus bit 11 DDR_A10 V16 O DDR VDD18_DDR DDR Address Bus bit 10 DDR_A9 U16 O DDR VDD18_DDR DDR Address Bus bit 09 DDR_A8 W17 O DDR VDD18_DDR DDR Address Bus bit 08 DDR_A7 T15 O DDR VDD18_DDR DDR Address Bus bit 07 DDR_A6 W16 O DDR VDD18_DDR DDR Address Bus bit 06 28 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM368 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
