DM368ZCEZ datasheet(65/208 Pages) TI1

65 / 208 page

TMS320DM368

www.ti.com

SPRS668C

– APRIL 2010 – REVISED JUNE 2011

Table 3-12. Device Configuration (continued)

Default Setting (by internal

Sampled

pull-up/

Device Configuration Input

Function

pull-down)

OSCCFG

Oscillator Configuration

GIO81

OSCCFG = '0' for mode #1

(Mode #1)

OSCCFG = '1' for mode #2

3.7.2

PLL Configuration

After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The

PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1

(typically 24 MHz) drives the chip after reset. For more information on device clocking, see Section 3.3 .

The default state of the PLLs is reflected in the default state of the register bits in the PLLC registers.

Refer to the TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).

3.7.3

Power Domain and Module State Configuration

Only a subset of modules are enabled after reset by default. Table 3-13 shows which modules are

enabled after reset. Table 3-13 shows that the following modules are enabled depending on the sampled

state of the device configuration pins. For example, if UART boot mode is BTSEL[2:0] = 011, then the

default state of the UART module is enabled. For more information on module configuration, refer to the

TMS320DM36x DMSoC ARM Subsystem Reference Guide (literature number SPRUFG5).

Table 3-13. LPSC Assignments and Module Configuration(1)

LPSC/

MODULE

MODULE NAME

BTSEL [2:0]

NUMBER

000

001

010

011

100

101

110

111

ROM

AEMIF

(MMC/SD0

ROM (HPI)

(NAND)

(UART0)

(USB)

(SPI0)

(EMAC)

)

EDMA CC

EDMA TC0

EDMA TC1

EDMA TC2

EDMA TC3

TIMER3

SPI1

MMC_SD1

McBSP

USB

PWM3

SPI2

RTO

DDR EMIF

AEMIF

MMC/SD0

Reserved

TIMER4

I2C

UART0

UART1

UHPI

(1)

"(Blank)" in the above table indicates module is disabled.

Device Configurations

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