CS61880 datasheet(40/70 Pages) CIRRUS

40 / 70 page

CS61880

DS450PP3

14.26 AWG Enable Register (19h)

14.27 Reserved Register (1Ah)

14.28 Reserved Register (1Bh)

14.29 Reserved Register (1Ch)

14.30 Reserved Register (1Dh)

14.31 Bits Clock Enable Register (1Eh)

14.32 Reserved Register (1Fh)

14.33 Status Registers

The following Status registers are read-only: LOS

Status Register (04h) (See Section 14.5 on

page 35), DFM Status Register (05h) (See Sec-

tion 14.6 on page 35) and AIS Status Register

(13h) (See Section 14.20 on page 38). The

CS61880 generates an interrupt on the INT pin any

time an unmasked status register bit changes.

BIT

NAME

Description

[7:0]

AWGN 7-0

The AWG enable register is used for selecting the source of the customized transmission

pulse-shape. Setting bit n to “1” in this register selects the AWG as the source of the output

pulse shape for channel n. When bit n is set to “0” the pre-programmed pulse shape in the

ROM is selected for transmission on channel n. (Refer to Arbitrary Waveform Generator

(See Section 15 on page 42). Register bits default to 00h after power-up or reset.

BIT

NAME

Description

[7:0]

RSVD 7-0

RESERVED

BIT

NAME

Description

[7:0]

RSVD 7-0

RESERVED

BIT

NAME

Description

[7:0]

RSVD 7-0

RESERVED

BIT

NAME

Description

[7:0]

RSVD 7-0

RESERVED

BIT

NAME

Description

[7:0]

BITS 7-0

Writing a “1” to bit n in this register changes channel n to a stand-alone timing recovery unit

used for G.703 clock recovery. (Refer to BUILDING INTEGRATED TIMING SYSTEMS

(BITS) CLOCK MODE (See Section 8 on page 23) for a better description of the G.703 clock

recovery function). Register bits default to 00h after power-up or reset.

BIT

NAME

Description

[7:0]

RSVD 7-0

RESERVED

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