8XC151SASB HIGH-PERFORMANCE CHMOS MICROCONTROLLER

Table 12 Programming and Verification Modes Mode

8XC151SASB

Addresses

Mode

PROG

P0

P2

P1 (high) P3 (low)

Notes

X e 7X e 3

Program On-Chip Code

Y

5 Pulses

68H

Data

0000H – 3FFFH (16K)

1

Memory

0000H – 1FFFH (8K)

Verify On-Chip Code

Y

Y

High

28H

Data

0000H – 3FFFH (16K)

Memory

0000H – 1FFFH (8K)

Program Configuration

2

Bytes

Verify Configuration

2

Bytes

Program Lock Bits

Y

25 Pulses

6BH

XX

0001H – 0003H

1 3

Verify Lock Bits

Y

Y

High

2BH

Data

0000H

4

Program Encryption

Y

25 Pulses

6CH

Data

0000H – 007FH

1

Array

Verify Signature Bytes

Y

Y

High

29H

Data

0030H 0031H 0060H

NOTES

1 The PROG

pulse waveform is shown in Figure 19

2 Factory-programmed ROM and OTPROM versions of 8XC151SASB use configuration byte information supplied in a

separate hexadecimal disk file 8XC151SASB devices without internal ROMOTPROM arrays fetch configuration byte

information from external application memory based on an internal address range of FFF98H

3 When programming the lock bits the data bits on port 2 are don’t care Identify the lock bits with the address as follows

LB3 - 0003H LB2 - 0002H LB1 - 0001H

4 The three lock bits are verified in a single operation The states of the lock bits appear simultaneously at port 2 as

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