Nexperia

74LVC30A

8-input NAND gate

5. Pinning information

5.1. Pinning

74LVC30

A

B

n.c.

C

H

D

G

E

n.c.

F

n.c.

GND

Y

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1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration SO14 and TSSOP14

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74LVC30A

Transparent top view

F

n.c.

E

n.c.

D

G

C

H

B

n.c.

6

9

5

10

4

11

3

12

2

13

terminal 1

index area

(1) This is not a supply pin. The substrate is

attached to this pad using conductive die attach

material. There is no electrical or mechanical

requirement to solder this pad.However, if it is

soldered, the solder land should remain floating or

be connected to GND.

Fig. 5. Pin configuration for DHVQFN14

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

A, B, C, D, E, F, G, H

1, 2, 3, 4, 5, 6, 11, 12

data input

GND

7

ground (0 V)

Y

8

data output

n.c.

9, 10, 13

not connected

14

supply voltage

74LVC30A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 15 March 2019

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