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74LVC30AD Datasheet(PDF) 6 Page - Nexperia B.V. All rights reserved

Part # 74LVC30AD
Description  8-input NAND gate
PDF  13 Pages
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Manufacturer  NEXPERIA [Nexperia B.V. All rights reserved]
Direct Link  https://www.nexperia.com/
Logo NEXPERIA - Nexperia B.V. All rights reserved

74LVC30AD Datasheet(HTML) 6 Page - Nexperia B.V. All rights reserved

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Nexperia
74LVC30A
8-input NAND gate
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit, see Fig. 7.
-40 °C to +85 °C
-40 °C to +125 °C
Symbol Parameter
Conditions
Min
Typ[1]
Max
Min
Max
Unit
A, B, C, D, E, F, G, H to Y;
see Fig. 6
[2]
VCC = 1.2 V
-
13.2
-
-
-
ns
VCC = 1.65 V to 1.95 V
2.2
5.9
11.6
2.2
12.3
ns
VCC = 2.3 V to 2.7 V
1.6
3.9
7.3
1.6
7.9
ns
VCC = 2.7 V
1.5
4.1
7.3
1.5
7.8
ns
tpd
propagation delay
VCC = 3.0 V to 3.6 V
1.4
3.6
6.3
1.4
6.8
ns
per gate; VI = GND to VCC
[3]
VCC = 1.65 V to 1.95 V
-
12.5
-
-
-
pF
VCC = 2.3 V to 2.7 V
-
13.5
-
-
-
pF
CPD
power dissipation
capacitance
VCC = 3.0 V to 3.6 V
-
15.5
-
-
-
pF
[1] Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD x VCC2 x fi x N + Σ(CL x VCC2 x fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volt;
N = number of inputs switching;
Σ(CL x VCC2 x fo) = sum of the outputs.
10.1. Waveform and test circuit
aaa-013467
VM
GND
VI
VOH
Y output
A, B, C, D,
E, F, G, H
input
VOL
tPHL
tPLH
VM
VM = 1.5 V at VCC ≥ 2.7 V
VM = 0.5 x VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig. 6. Input (A, B, C, D, E, F, G, H) to output (Y) propagation delays
74LVC30A
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2019. All rights reserved
Product data sheet
Rev. 2 — 15 March 2019
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