2.5V or 3.3V, 200-MHz, 12-Output
Zero Delay Buffer
CY29772
Cypress Semiconductor Corporation
•
198 Champion Court
•
San Jose
, CA 95134-1709
•
408-943-2600
Document #: 38-07572 Rev. *A
Revised September 1, 2005
Features
• Output frequency range: 8.33 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 125 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2% max. Output duty cycle variation
• 7 ps RMS typical Cycle-to-cycle jitter
• 6 ps RMS typical Period jitter
• 12 clock outputs: drive up to 24 clock lines
• One feedback output
• Three reference clock inputs: crystal or LVCMOS
• 300 ps max. output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9772 and MPC972
• Industrial temperature range: –40°C to +85°C
• 52-pin 1.0-mm TQFP package
Description
The CY29772 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high-speed
clock-distribution applications.
The CY29772 features one on-chip crystal oscillator and two
LVCMOS reference clock inputs and provides 12 outputs parti-
tioned in three banks of four outputs each. Each bank divides
the VCO output per SEL(A:C) settings, see Functional Table.
These dividers allow output to input ratios of 8:1, 6:1, 5:1, 4:1,
3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each
LVCMOS-compatible output can drive 50
Ω series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces,
giving the device an effective fanout of 1:24.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Block Diagram
Pin Configuration
AVSS
MR#/OE
SCLK
SDA TA
FB_SEL2
PLL_EN
REF_SEL
TCLK_SEL
TCLK0
TCLK1
XIN
XOUT
AVDD
VSS
QB0
V DDQB
QB1
VSS
QB2
V DDQB
QB3
FB_IN
VSS
FB_OUT
VDD
FB_SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
52 51 50 49 48 47 46 45 44 43 42 41 40
C Y29772
REF_SEL
0
1
0
1
Phase
Detector
VCO
LPF
Sync
Frz
D Q
QA0
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
Sync
Frz
D Q
0
1
/2
Power-On
Reset
Output Disable
Circuitry
Data Generator
/4, /6, /8, /12
/4, /6, /8, /10
/2, /4, /6, /8
/4, /6, /8, /10
Sync Pulse
XIN
XOUT
TCLK0
TCLK1
TCLK_SEL
FB_IN
FB_SEL2
MR#/OE
SELA(0,1)
2
SELB(0,1)
2
SELC(0,1)
2
FB_SEL(0,1)
2
SCLK
SDATA
INV_CLK
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
12
VCO_SEL
PLL_EN
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