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LSM6DSOP Datasheet(PDF) 24 Page - STMicroelectronics |
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LSM6DSOP Datasheet(HTML) 24 Page - STMicroelectronics |
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24 / 107 page  Module specifications LSM6DSOP 24/107 DocID032926 Rev 5 4.4.2 I²C - inter-IC control interface Subject to general operating conditions for Vdd and Top. Figure 6. I²C slave timing diagram Note: Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both ports. Table 7. I²C slave timing values Symbol Parameter I²C standard mode(1) I²C fast mode (1) Unit Min Max Min Max f(SCL) SCL clock frequency 0 100 0 400 kHz tw(SCLL) SCL clock low time 4.7 1.3 μs tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 ns th(SDA) SDA data hold time 0 3.45 0 0.9 μs th(ST) START condition hold time 4 0.6 μs tsu(SR) Repeated START condition setup time 4.7 0.6 tsu(SP) STOP condition setup time 4 0.6 tw(SP:SR) Bus free time between STOP and START condition 4.7 1.3 1. Data based on standard I²C protocol requirement, not tested in production. |
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