VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

13

POST OFFICE BOX 655303

REGISTER DEFINITION

video control register (06H)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

X

X

X

X

X

X

X

MOD

X

video control register description

BIT

NAME

DESCRIPTION

D9–D2

X

Reserved

D1

MOD

This bit defines the mode of the input

0 = CCD mode (default)

1 = Video mode

D0

X

Reserved. Always program this bit to 0.

Default register value= 00 0000 0000

SR and ADCCLK internal delay register format (08H)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

ADCL4

ADCL3

ADCL2

ADCL1

ADCL0

SRL4

SRL3

SRL2

SRL1

SRL0

SR and ADCCLK internal delay register description

BIT

NAME

DESCRIPTION

D9–D5

ADCL4–ADCL0

These five bits set the internal ADCCLK delay. T is the period of the MCLK.

ADCL4

ADCL3

ADCL2

ADCL1

ADCL0

Typical internal delay

0

0000

0

0

0001

T/30

:

0

0111

7T/30 (default)

:

1

1101

29T/30

D4–D0

SRL4–SRL0

These five bits set the internal SR delay. T is the period of the MCLK.

SRL4

SRL3

SRL2

SRL1

SRL0

Typical internal delay

0

0000

0

0

0001

T/30

:

0

1001

9T/30 (default)

:

1

1

1

0

1

29T/30

Default register value= 0 01110 1001

NOTE: Do not program SR and ADCCLK internal delays above 29T/30.