VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

17

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

SOFTWARE/HARDWARE

GLOBAL STANDBY

PDD1/PDD2

DACD

STATUS OF

DAC1/DAC2

Active

0

x

Active

Active

1

x

Standby

Standby

0

0

Standby

Standby

0

1

Active

Standby

1

x

Standby

NOTE: The hardware global standby is set by pulling down terminal 44 (STBY) of the

VSP10T21 device. The software global standby is controlled by setting bit D9

(STBY) in the control register to 1.

3-wire serial interface

A simple 3-wire (terminals 48 (SCLK), 47 (SDIN), and 46 (CS)) serial interface is provided to allow writing to

the internal registers of the VSP10T21 device. The serial clock SCLK can be run at a maximum speed of

40 MHz. The serial data SDIN is 16 bits long. After two leading null bits, there are four address bits for which

internal register is to be updated, the following 10 bits are the data to be written to the register. To enable the

serial port, CS must be held low. The data transfer is initiated by the incoming SCLK after CS falls. Figure 3

shows the detailed timing for the serial interface.

The SCLK polarity is selectable by pulling terminal 45 (SCKP) either high or low.

device reset

The device is not under the default configuration when powered on. The registers are set to the default value

by a reset. When terminal 43 (RESET) is pulled low, all internal registers are set to their default values. In

addition, the VSP10T21 device has a software-reset function that resets the device when writing to a control

bit in the control register.

See REGISTER DEFINITION for the register default values.

power-down mode (standby)

The VSP10T21 device implements both hardware and software power-down modes. Pulling terminal 44

(STBY) low puts the device in the low-power standby mode. The total power drops to about 1.5 mW. Setting

bit D9 (STBY) in the control register can also activate the power-down mode. Users can still program all internal

registers during the power-down mode.

power supply

The VSP10T21 device has several power supply terminals. Each major internal analog block has a dedicated

requiring different supply voltages.