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PCF2127AT Datasheet(PDF) 45 Page - NXP Semiconductors |
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PCF2127AT Datasheet(HTML) 45 Page - NXP Semiconductors |
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45 / 100 page ![]() PCF2127 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 8 — 19 December 2014 45 of 100 NXP Semiconductors PCF2127 Accurate RTC with integrated quartz crystal for industrial applications If a new value of n is written before the end of the actual timer period, this value takes immediate effect. It is not recommended to change n without first disabling the counter by setting WD_CD[1:0] = 00. The update of n is asynchronous to the timer clock. Therefore changing it on the fly could result in a corrupted value loaded into the countdown counter. This can result in an undetermined countdown period for the first period. The countdown value n will, however, be correctly stored and correctly loaded on subsequent timer periods. If this mode is enabled and the countdown timer flag CDTF is set, an interrupt signal on INT will be generated. See Section 8.13.2 for details on how the interrupt can be controlled. When starting the countdown timer for the first time, only the first period will not have a fixed duration. The amount of inaccuracy for the first timer period depends on the chosen source clock, see Table 60. At the end of every countdown, the timer sets the countdown timer flag (CDTF). CDTF may only be cleared by command. The asserted CDTF can be used to generate an interrupt (INT). The interrupt may be generated as a pulsed signal every countdown period or as a permanently active signal which follows the condition of CDTF. TI_TP is used to control this mode selection. The interrupt output may be disabled with the CDTIE bit, see Table 9. In this example, it is assumed that the countdown timer flag (CDTF) is cleared before the next countdown period expires and that INT is set to pulsed mode. Fig 25. General countdown timer behavior Table 60. First period delay for timer counter Timer source clock Minimum timer period Maximum timer period 4.096 kHz n n + 1 64 Hz n n + 1 1 Hz (n 1) + 1⁄ 64 Hz n + 1⁄64 Hz 1⁄60 Hz (n 1) + 1⁄ 64 Hz n + 1⁄64 Hz |
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